Here is the toplevel schematic:
The 15-bit synchronous counter is here:
Each prescaler has a disable input. If this input goes high, the prescaler feeds its inout to all outputs without prescaling. This disable inputs are connected to the Enable input through an inverter. The enable input is connected to bit 8 of the CAMAC output bit pattern and thus controllable by the frontend program. This his handy if one wants to debug the electronics. If one turns prescaling off, one gets much more triggers, thus helping the scope monitoring of signals.
CAMAC bit 7 selects two different prescaling levels for the pion gate used for the pienuHi trigger, so one can change the prescaling ratio without reprogramming the LB500.
